A research collaboration led by Stanford University has produced what researchers describe as the first truly monolithic 3D chip manufactured at a commercial US foundry, a milestone that could reshape how future processors are built.
The experimental chip was fabricated at SkyWater Technology’s US facility and stacks logic and memory directly on top of each other on a single die, rather than placing them side by side in a traditional flat layout. By shortening the physical distance between compute and memory, the design dramatically reduces data movement, one of the biggest bottlenecks in modern chips.
According to details reported by Tom’s Hardware, the prototype integrates silicon CMOS logic, resistive RAM, and carbon nanotube field effect transistors using a low-temperature fabrication process that prevents damage to lower layers. All components were built sequentially on the same wafer, creating dense vertical connections instead of relying on packaging-level stacking.
The chip was produced on SkyWater’s mature 90 to 130 nanometer process, proving that advanced architectural gains do not require cutting-edge lithography. Despite the older node, early hardware testing showed roughly a four times performance improvement over comparable two-dimensional designs operating at similar size and latency.
Simulations suggest the gains could scale much further. When researchers modeled taller stacks with additional layers of memory and compute, performance improvements reached up to twelve times on AI-style workloads, including models based on Meta’s LLaMA architecture. The team estimates that continued vertical scaling could eventually deliver 100 to 1,000 times improvement in energy-delay product, a key metric that combines speed and efficiency.
Carbon nanotube transistors play a critical role in enabling the stack. They operate effectively at lower temperatures than conventional silicon transistors, allowing multiple device layers to be fabricated without degrading previously built circuits. This makes true monolithic 3D integration practical rather than purely experimental.
Unlike earlier academic demonstrations built in specialized university cleanrooms, this chip was produced entirely within a commercial foundry environment. SkyWater executives involved in the project said this proves monolithic 3D chips can transition from research labs into domestic manufacturing pipelines.
The work was presented at the IEEE International Electron Devices Meeting in December and is being viewed as a potential path forward as traditional transistor scaling slows. Instead of making chips smaller and hotter, the future may involve building them upward, layer by layer.
